MC68HC11P2 Datasheet, PDF (220/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
CPU Core and Instruction Set
11.3.6.8 Stop disable (S)
Setting the STOP disable (S) bit prevents the STOP instruction from
putting the M68HC11 into a low-power stop condition. If the STOP
instruction is encountered by the CPU while the S-bit is set, it is treated
as a no-operation (NOP) instruction, and processing continues to the
next instruction. S is set by reset — i.e. STOP is disabled by default.
11.4 Data types
The M68HC11 CPU supports the following data types:
• Bit data
• 8-bit and 16-bit signed and unsigned integers
• 16-bit unsigned fractions
• 16-bit addresses
A byte is eight bits wide and can be accessed at any byte location. A
word is composed of two consecutive bytes with the most significant
byte at the lower value address. Because the M68HC11 is an 8-bit CPU,
there are no special requirements for alignment of instructions or
operands.
11.5 Opcodes and operands
The M68HC11 family of microcontrollers uses 8-bit opcodes. Each
opcode identifies a particular instruction and associated addressing
mode to the CPU. Several opcodes are required to provide each
instruction with a range of addressing capabilities. Only 256 opcodes
would be available if the range of values were restricted to the number
able to be expressed in 8-bit binary numbers.
A four-page opcode map has been implemented to expand the number
of instructions. An additional byte, called a prebyte, directs the processor
from page 0 of the opcode map to one of the other three pages. As its
Technical Data
CPU Core and Instruction Set
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MC68HC11P2 — Rev 1.0