MC68HC11P2 Datasheet, PDF (222/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
CPU Core and Instruction Set
11.6.3 Extended (EXT)
In the extended addressing mode, the effective address of the argument
is contained in two bytes following the opcode byte. These are three-
byte instructions (or four-byte instructions if a prebyte is required). One
or two bytes are needed for the opcode and two for the effective address.
11.6.4 Indexed (IND, X; IND, Y)
In the indexed addressing mode, an 8-bit unsigned offset contained in
the instruction is added to the value contained in an index register (IX or
IY) — the sum is the effective address. This addressing mode allows
referencing of any memory location in the 64kbyte address space.
These are two- to five-byte instructions, depending on whether or not a
prebyte is required.
11.6.5 Inherent (INH)
In the inherent addressing mode, all the information necessary to
execute the instruction is contained in the opcode. Operations that use
only the index registers or accumulators, as well as control instructions
with no arguments, are included in this addressing mode. These are one
or two-byte instructions.
11.6.6 Relative (REL)
The relative addressing mode is used only for branch instructions. If the
branch condition is true, an 8-bit signed offset included in the instruction
is added to the contents of the program counter to form the effective
branch address. Otherwise, control proceeds to the next instruction.
These are usually two-byte instructions.
Technical Data
CPU Core and Instruction Set
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MC68HC11P2 — Rev 1.0