MC68HC11P2 Datasheet, PDF (206/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Resets and Interrupts
Power-on reset
(POR)
Highest
External
reset
Delay
(4064 cycles)
Priority
Clock monitor fail
(CME = 1)
Load program counter
with contents of
$FFFE, $FFFF
(vector fetch)
Load program counter
with contents of
$FFFC, $FFFD
(vector fetch)
Lowest
COP watchdog
timeout
(NOCOP = 0)
Load program counter
with contents of
$FFFA, $FFFB
(vector fetch)
Set S, X, and I bits
in CCR.
Reset MCU hardware
1A
Begin an instruction
sequence
Yes
X-bit in
CCR set?
No
XIRQ pin
low?
No
1B
Stack CPU registers.
Yes
Set X and I bits.
Fetch vector at
$FFF4, $FFF5
Technical Data
Resets and Interrupts
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MC68HC11P2 — Rev 1.0