MC68HC11P2 Datasheet, PDF (239/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Electrical Specifications
Control timing
Internal
clocks
IRQ⁽¹⁾
IRQ⁽²⁾
or XIRQ
E clock
PW_IRQ
t_STOPDELAY(3)
Address⁽⁴⁾
SA⁽⁶⁾ SA+1
SA+1
Op-
code
Resume program with instruction which follows the STOP instruction
Address⁽⁵⁾
SA⁽⁶⁾ SA+1
Notes:
(1) Edge sensitive IRQ pin (IRQE = 1).
(2) Level sensitive IRQ pin (IRQE = 0).
(3) t_STOPDELAY = 4064 t_CYC (DLY = 1) or 4 t_CYC (DLY = 0).
New
SA+1 SA+2 SP… SP–7 SP–8 SP–8 FFF2 FFF3 _PC
(4) XIRQ with X-bit in CCR = 1.
(5) IRQ (or XIRQ, with X-bit = 0; in this case vector fetch will be $FFF4/5).
(6) SA = STOP address.
Figure 12-5. STOP recovery timing
E clock
IRQ, XIRQ,
or internal
interrupts
Address
R/W
t_PCSU
t_WRS
WA⁽¹⁾ WA+1
SP
SP–1 SP–2…SP–8 SP–8 SP–8…SP–8 SP–8 SP–8 SP–8 VA⁽²⁾ VA+1
New
PC
Stack registers
Notes:
RESET also causes recovery from WAIT.
(1) WA = WAIT address.
(2) VA = Vector address.
MC68HC11P2 — Rev 1.0
Electrical Specifications
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Technical Data