MC68HC11P2 Datasheet, PDF (117/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Motorola Interconnect Bus (MI BUS)
MI BUS clock rate
The MI BUS line can take two states, recessive or dominant. The
recessive state (‘1’) is represented by 5V, through a pull-up resistor of
10k¾. The dominant state (‘0’) is represented by a maximum 0.3V
(V_CESAT of the transistor, T1).
The bus load depends on the number of devices on the bus. Each device
has a pull-up resistor of 10k¾. An external termination resistor is used
to stabilize the load resistance of the bus at 600¾.
6.9 MI BUS clock rate
The MI BUS clock rate is set via the SCI baud registers. To use the
MI BUS the ST4XCK clock frequency that drives the SCI clock generator
must be selected to match the minimum resolution of the MI BUS logic.
This is expressed by the following formula:
ST4XCK = 16 • 2n • (2 • Push_field_bit_rate) = 16 • 2n • 40kHz =
n • 1280kHz
where ‘n’ is an integer and 20kHz is the minimum Push field bit rate for
the MI BUS. Values for ST4XCK could be 1280kHz, 2560kHz, …, n •
1280kHz. The value ‘n’ is the modulus for the MI BUS baud register (see
S2BDH, S2BDL — MI BUS clock rate control registers). The
ST4XCK may be the output of the PLL circuit or it may be the EXTAL
input of the MCU. This selection is made by setting the MCS bit which is
described in PLLCR — PLL control register.
6.10 SCI/MI BUS2 registers
MI BUS operation is controlled by the same group of registers as is used
for the SCI. However the function of some of the bits is modified when in
MI BUS mode. A description of the registers, as applicable to the
MI BUS function, is given here.
NOTE: Bits that have no meaning in MI BUS mode are shown shaded to avoid
confusion.
MC68HC11P2 — Rev 1.0
Motorola Interconnect Bus (MI BUS)
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Technical Data