MC68HC11P2 Datasheet, PDF (23/268 Pages) Motorola, Inc – Microcontrollers

2.4 RESET
Freescale Semiconductor, Inc.
Pin Descriptions
RESET
Bypassing requirements vary, depending on how heavily the MCU pins
are loaded.
The MC68HC11P2 MCU has five VDD pins and five VSS pins. One pair
of these pins is reserved for supplying power to the analog-to-digital
converter (VDD AD, VSS AD); two pairs are used for the internal logic
(VDD, VSS); the remaining two pairs supply power for the port logic on
either half of the chip (VDDL, VSSX and VDDR, VSSX). This
arrangement minimizes the injection of noise into the digital circuitry on
the chip.
An active low bidirectional control signal, RESET, acts as an input to
initialize the MCU to a known start-up state. It also acts as an open-drain
output to indicate that an internal failure has been detected in either the
clock monitor or the COP watchdog circuit. The CPU distinguishes
between internal and external reset conditions by sensing whether the
reset pin rises to a logic one in less than six E clock cycles after a reset
has occurred. It is therefore not advisable to connect an external
resistor-capacitor (RC) power-up delay circuit to the reset pin of
M68HC11 devices because the circuit charge time constant can cause
the device to misinterpret the type of reset that occurred. Refer to
Resets and Interrupts for further information.
Figure 2-2 illustrates a typical reset circuit that includes an external
switch together with a low voltage inhibit circuit, to prevent power
transitions, or RAM or EEPROM corruption.
MC68HC11P2 — Rev 1.0
Pin Descriptions
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Technical Data