MC68HC11P2 Datasheet, PDF (240/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Electrical Specifications
12.7.1 Peripheral port timing
(V_DD = 5.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = T_L to T_H)
Characteristic ⁽¹⁾
2.0 MHz
3.0 MHz
Symbol
Min. Max. Min. Max.
Frequency of operation (E clock frequency) f_OP
0
2.0
0
3.0
E clock period
t_CYC 500
—
333
—
Peripheral data set-up time, all ports ⁽²⁾
t_PDSU 100
—
100
—
Peripheral data hold time, all ports ⁽²⁾
t_PDH
50
—
50
—
Delay time, peripheral data write
MCU write to port A, B, G or H
MCU write to port C, D or F
t_PWD
— 200 — 200
— 225 — 183
4.0 MHz
Min. Max.
0
4.0
250 —
100 —
50
—
— 200
— 162
Unit
MHz
ns
ns
ns
ns
1. All timing is given with respect to 20% and 70% of V_DD, unless otherwise noted.
2. Port C and D timing is valid for active drive (CWOM and DWOM bits clear in OPT2 and SPCR registers, respectively).
E clock
Ports
A, C, D, F
Ports
B, E, G, H
MCU read of port
t_PDSU
t_PDH
t_PDSU
t_PDH
Figure 12-7. Port read timing diagram
E clock
Ports
C, D, F
Ports
A, B, G, H
MCU write to port
t_PWD
Previous port data
Previous port data
New data valid
t_PWD
New data valid
Figure 12-8. Port write timing diagram
Technical Data
Electrical Specifications
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MC68HC11P2 — Rev 1.0