MC68HC11P2 Datasheet, PDF (229/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
CPU Core and Instruction Set
Instruction set
Table 11-2. Instruction set (Sheet 7 of 8)
Mnemonic
SBCB (opr)
Operation
Subtract with carry from B
SEC
SEI
SEV
STAA (opr)
Set carry
Set interrupt mask
Set overflow flag
Store accumulator A
STAB (opr)
Store accumulator B
STD (opr)
Store accumulator D
STOP
STS (opr)
Stop internal clocks
Store stack pointer
STX (opr)
Store index register X
STY (opr)
Store index register Y
SUBA (opr) Subtract memory from A
SUBB (opr) Subtract memory from B
SUBD (opr) Subtract memory from D
Description
B–M–C⇒B
1⇒C
1⇒I
1⇒V
A⇒M
B⇒M
A ⇒ M; B ⇒ M+1
—
SP ⇒ M:M+1
IX ⇒ M:M+1
IY ⇒ M:M+1
A–M⇒A
B–M⇒B
D – M:M+1 ⇒ D
Addressing
mode
B IMM
B DIR
B EXT
B IND, X
B IND, Y
INH
INH
INH
A DIR
A EXT
A IND, X
A IND, Y
B DIR
B EXT
B IND, X
B IND, Y
DIR
EXT
IND, X
IND, Y
INH
DIR
EXT
IND, X
IND, Y
DIR
EXT
IND, X
IND, Y
DIR
EXT
IND, X
IND, Y
A IMM
A DIR
A EXT
A IND, X
A IND, Y
B IMM
B DIR
B EXT
B IND, X
B IND, Y
IMM
DIR
Opcode
C2
D2
F2
E2
18 E2
0D
0F
0B
97
B7
A7
18 A7
D7
F7
E7
18 E7
DD
FD
ED
18 ED
CF
9F
BF
AF
18 AF
DF
FF
EF
CDEF
18 DF
18 FF
1A EF
18 EF
80
90
B0
A0
18 A0
C0
D0
F0
E0
18 E0
83
93
Instruction
Operand
ii
dd
hh ll
ff
ff
—
—
—
dd
hh ll
ff
ff
dd
hh ll
ff
ff
dd
hh ll
ff
ff
—
dd
hh ll
ff
ff
dd
hh ll
ff
ff
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
Cycles
2
3
4
4
5
2
2
2
3
4
4
5
3
4
4
5
4
5
5
6
2
4
5
5
6
4
5
5
6
5
6
6
6
2
3
4
4
5
2
3
4
4
5
4
5
Condition codes
SXH I NZVC
————∅∅∅∅
——————— 1
——— 1 ————
—————— 1 —
————∅∅ 0 —
————∅∅ 0 —
————∅∅ 0 —
————————
————∅∅ 0 —
————∅∅ 0 —
————∅∅ 0 —
————∅∅∅∅
————∅∅∅∅
————∅∅∅∅
MC68HC11P2 — Rev 1.0
CPU Core and Instruction Set
For More Information On This Product,
Go to: www.freescale.com
Technical Data