MC68HC11P2 Datasheet, PDF (230/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
CPU Core and Instruction Set
Table 11-2. Instruction set (Sheet 8 of 8)
Mnemonic
SWI
TAB
TAP
TBA
TEST
TPA
TST (opr)
TSTA
TSTB
TSX
TSY
TXS
TYS
WAI
XGDX
XGDY
Operation
Software interrupt
Transfer A to B
Transfer A to CC register
Transfer B to A
Test (only in test modes)
Transfer CC register to A
Test for zero or minus
Test A for zero or minus
Test B for zero or minus
Transfer stack pointer to X
Transfer stack pointer to Y
Transfer X to stack pointer
Transfer Y to stack pointer
Wait for interrupt
Exchange D with X
Exchange D with Y
Description
Addressing
mode
see Figure 11-2
INH
A⇒B
INH
A ⇒ CCR
INH
B⇒A
INH
address bus increments INH
CCR ⇒ A
INH
M –0
EXT
IND, X
IND, Y
A–0
A INH
B–0
B INH
SP + 1 ⇒ IX
INH
SP + 1 ⇒ IY
INH
IX – 1 ⇒ SP
INH
IY – 1 ⇒ SP
INH
stack registers & WAIT INH
IX ⇒ D; D ⇒ IX
INH
IY ⇒ D; D ⇒ IY
INH
Opcode
3F
16
06
17
00
07
7D
6D
18 6D
4D
5D
30
18 30
35
18 35
3E
8F
18 8F
Instruction
Operand
—
—
—
—
—
—
hh ll
ff
ff
—
—
—
—
—
—
—
—
—
Cycles
14
2
2
2
†
2
6
6
7
2
2
3
4
3
4
‡
3
4
Condition codes
SXH I NZVC
——— 1 ————
————∅∅ 0 —
∅ ↓ ∅∅∅∅∅∅
————∅∅ 0 —
————————
————————
————∅∅ 0 0
————∅∅ 0 0
————∅∅ 0 0
————————
————————
————————
————————
————————
————————
————————
Operators
⇒ Is transferred to
• Boolean AND
+ Arithmetic addition, except where used as an
inclusive-OR symbol in Boolean formulae
⊕ Exclusive-OR
* Multiply
: Concatenation
– Arithmetic subtraction, or negation symbol
(Twos complement)
Operands
dd 8-bit direct address ($0000–$00FF); the high byte is assumed
to be zero
ff 8-bit positive offset ($00 to $FF (0 to 256)) is added to the
contents of the index register
hh High order byte of 16-bit extended address
ii One byte of immediate data
jj High order byte of 16-bit immediate data
kk Low order byte of 16-bit immediate data
ll Low order byte of 16-bit extended address
mm 8-bit mask (set bits to be affected)
rr Signed relative offset ($80 to $7F (–128 to +127));
offset is relative to the address following the offset byte
Cycles
† Infinite, or until reset occurs
‡ 12 cycles are used, beginning with the opcode
fetch. A wait state is entered, which remains
in effect for an integer number of MPU E clock
cycles (n) until an interrupt is recognized.
Finally, two additional cycles are used to fetch
the appropriate interrupt vector. (14 + n, total).
Condition Codes
— Bit not changed
0 Bit always cleared
1 Bit always set
∅ Bit set or cleared, depending on the operation
↓ Bit can be cleared, but cannot become set
? Not defined
Technical Data
CPU Core and Instruction Set
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MC68HC11P2 — Rev 1.0