MC68HC11P2 Datasheet, PDF (221/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
CPU Core and Instruction Set
Addressing modes
A complete instruction consists of a prebyte, if any, an opcode, and zero,
one, two, or three operands. The operands contain information the CPU
needs for executing the instruction. Complete instructions can be from
one to five bytes long.
11.6 Addressing modes
Six addressing modes (immediate, direct, extended, indexed, inherent
and relative) are detailed in the following paragraphs and can be used to
access memory. All modes except inherent mode use an effective
address. The effective address is the memory address from which the
argument is fetched or stored, or the address from which execution is to
proceed. The effective address can be specified within an instruction, or
it can be calculated.
11.6.1 Immediate (IMM)
In the immediate addressing mode an argument is contained in the
byte(s) immediately following the opcode. The number of bytes following
the opcode matches the size of the register or memory location being
operated on. There are two, three and four (if prebyte is required) byte
immediate instructions. The effective address is the address of the byte
following the instruction.
11.6.2 Direct (DIR)
In the direct addressing mode, the low-order byte of the operand
address is contained in a single byte following the opcode, and the high-
order byte of the address is assumed to be $00. Addresses $00–$FF are
thus accessed directly, using two-byte instructions. Execution time is
reduced by eliminating the additional memory access required for the
high-order address byte. In most applications, this 256-byte area is
reserved for frequently referenced data. In M68HC11 MCUs, the
memory map can be configured for combinations of internal registers,
RAM, or external memory to occupy these addresses.
MC68HC11P2 — Rev 1.0
CPU Core and Instruction Set
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Technical Data