MC68HC11P2 Datasheet, PDF (58/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Table 3-6. EEPROM remapping
EE[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Location
$0D80–$0FFF
$1D80–$1FFF
$2D80–$2FFF
$3D80–$3FFF
$4D80–$4FFF
$5D80–$5FFF
$6D80–$6FFF
$7D80–$7FFF
$8D80–$8FFF
$9D80–$9FFF
$AD80–$AFFF
$BD80–$BFFF
$CD80–$CFFF
$DD80–$DFFF
$ED80–$EFFF
$FD80–$FFFF
M3DL1, M3DL0, M2DL1, M2DL0 — MI BUS delay select (refer to
Motorola Interconnect Bus (MI BUS))
3.5.2.4 OPTION — System configuration options register 1
System config. options 1
(OPTION)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0039 ADPU CSEL IRQE DLY CME FCME CR1 CR0 0001 0000
The 8-bit special-purpose OPTION register sets internal system
configuration options during initialization. The time protected control bits,
IRQE, DLY, FCME and CR[1:0] can be written only once in the first 64
cycles after a reset and then they become read-only bits. This minimizes
the possibility of any accidental changes to the system configuration.
They may be written at any time in special modes.
ADPU — A/D power-up (refer to Analog-to-Digital Converter)
Technical Data
Operating Modes and On-Chip Memory
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MC68HC11P2 — Rev 1.0