MC68HC11P2 Datasheet, PDF (80/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Parallel Input/Output
4.7.1 PORTE — Port E data register
Port E data (PORTE)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$000A PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 undefined
This is a read-only register and is not affected by reset. The bits may be
read at any time.
NOTE:
As port E shares pins with the A/D converter, a read of the this register
may affect any conversion currently in progress, if it coincides with the
sample portion of the conversion cycle. Hence, normally port E should
not be read during the sample portion of any conversion.
4.8 Port F
Port F is an 8-bit bidirectional port, with both data and data direction
registers. In addition to their I/O capability, port F pins are used as the
non-multiplexed low order address pins, as shown in the following
table.
Pin
Alternate
function
PF0
A0

PF1
A1


PF2
PF3
PF4
A2
A3
A4



In expanded or test
mode, the pins become


the low order address
 _{and port F is not included}
PF5
A5


in the memory map.
PF6
A6


PF7
A7

The state of the pins on reset is mode dependent. In single chip or
bootstrap mode, port F pins are high-impedance inputs with selectable
internal pull-up resistors (see Internal pull-up/pull-down resistors). In
expanded or test modes, port F pins are low order address outputs and
PORTF/DDRF are not in the memory map.
Technical Data
Parallel Input/Output
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MC68HC11P2 — Rev 1.0