MC9S12Q128_10 Datasheet, PDF (89/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

2.3.2.3.3
Chapter 2 Port Integration Module (PIM9C32) Block Description
Port M Data Direction Register (DDRM)
Module Base + 0x0012
7
R
0
W
Reset
—
Read: Anytime.
Write: Anytime.
6
5
4
3
2
0
DDRM5
DDRM4
DDRM3
DDRM2
—
0
0
0
0
= Unimplemented or Reserved
Figure 2-19. Port M Data Direction Register (DDRM)
Table 2-17. DDRM Field Descriptions
1
DDRM1
0
0
DDRM0
0
Field
Description
5–0
DDRM[5:0]
Data Direction Port M — This register configures each port S pin as either input or output
If SPI or MSCAN is enabled, the SPI and MSCAN modules determines the pin directions. Please refer to the SPI
and MSCAN Block User Guides for details.
If the associated SCI or MSCAN transmit or receive channels are enabled, this register has no effect on the pins.
The pins are forced to be outputs if the SCI or MSCAN transmit channels are enabled, they are forced to be inputs
if the SCI or MSCAN receive channels are enabled.
The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTM
or PTIM registers, when changing the DDRM register.
Freescale Semiconductor
MC9S12Q128
89
Rev 1.10