MC9S12Q128_10 Datasheet, PDF (65/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family)
1.8 Recommended Printed Circuit Board Layout
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
• Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins.
• Central point of the ground star should be the V_SSR pin.
• Use low ohmic low inductance connections between V_SS1, V_SS2, and V_SSR.
• V_SSPLL must be directly connected to V_SSR.
• Keep traces of V_SSPLL, EXTAL, and XTAL as short as possible and occupied board area for C6,
C7, C11, and Q1 as small as possible.
• Do not place other signals or supplies underneath area occupied by C6, C7, C5, and Q1 and the
connection area to the MCU.
• Central power input should be fed in at the V_DDA/V_SSA pins.
Table 1-12. Recommended Component Values
Component
Purpose
Type
Value
C1
V_DD1 filter capacitor
Ceramic X7R
220nF, 470nF⁽¹⁾
C2
V_DDR filter capacitor
X7R/tantalum
>=100nF
C3
V_DDPLL filter capacitor
Ceramic X7R
100nF
C4
PLL loop filter capacitor
C5
PLL loop filter capacitor
See PLL specification chapter
C6
OSC load capacitor
C7
OSC load capacitor
See PLL specification chapter
C8
V_DD2 filter capacitor (80 QFP only)
Ceramic X7R
220nF
C9
V_DDA filter capacitor
Ceramic X7R
100nF
C10
V_DDX filter capacitor
X7R/tantalum
>=100nF
C11
DC cutoff capacitor
Colpitts mode only, if recommended by
quartz manufacturer
R1
Pierce Mode Select Pullup
Pierce Mode Only
R2
PLL loop filter resistor
See PLL Specification chapter
R3 / R_B
R4 / R_S
PLL loop filter resistor
PLL loop filter resistor
Pierce mode only
Q1
Quartz
—
—
1. In 48LQFP and 52LQFP package versions, V_DD2 is not available. Thus 470nF must be connected to
V_DD1.
Freescale Semiconductor
MC9S12Q128
65
Rev 1.10