MC9S12Q128_10 Datasheet, PDF (610/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Appendix A Electrical Characteristics
A.2 ATD Characteristics
This section describes the characteristics of the analog-to-digital converter.
V_RL is not available as a separate pin in the 48- and 52-pin versions. In this case the internal V_RL pad is
bonded to the V_SSA pin.
The ATD is specified and tested for both the 3.3V and 5V range. For ranges between 3.3V and 5V the ATD
accuracy is generally the same as in the 3.3V range but is not tested in this range in production test.
A.2.1 ATD Operating Characteristics In 5V Range
The Table A-10 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results: V_SSA ≤ V_RL ≤ V_IN ≤ V_RH ≤ V_DDA.
This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that
it ties to. If the input level goes outside of this range it will effectively be clipped.
Table A-10. ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted. Supply Voltage 5V-10% <= V_DDA <=5V+10%
Num C
Rating
Symbol
Min
Typ
Max
Unit
Reference Potential
1D
2
C Differential Reference Voltage⁽¹⁾
Low
V_RL
High
V_RH
V_SSA
—
V_DDA/2
V
V_DDA/2
—
V_DDA
V
V_RH-V_RL
4.75
5.0
5.25
V
3 D ATD Clock Frequency
f_ATDCLK
0.5
—
2.0
MHz
ATD 10-Bit Conversion Period
4D
Clock Cycles⁽²⁾ N_CONV10
14
—
28
Cycles
Conv, Time at 2.0MHz ATD Clock f_ATDCLK T_CONV10
7
—
14
µs
ATD 8-Bit Conversion Period
5D
Clock Cycles² N_CONV10
12
—
26
Cycles
Conv, Time at 2.0MHz ATD Clock f_ATDCLK T_CONV10
6
—
13
µs
5
D Recovery Time (V_DDA=5.0 Volts)
t_REC
—
—
20
µs
6 P Reference Supply current
I_REF
1. Full accuracy is not guaranteed when differential voltage is less than 4.75V
—
—
0.375
mA
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
610
MC9S12Q128
Freescale Semiconductor
Rev 1.10