MC9S12Q128_10 Datasheet, PDF (208/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 7 Debug Module (DBGV1) Block Description
Table 7-15. DBGC3 Field Descriptions (continued)
Field
1
RWBEN
0
RWB
Description
Read/Write Comparator B Enable Bit — The RWBEN bit controls whether read or write comparison is enabled
for comparator B. See Section 7.4.2.1.1, “Read or Write Comparison,” for more information. This bit is not useful
for tagged operations.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
Read/Write Comparator B Value Bit — The RWB bit controls whether read or write is used in compare for
comparator B. The RWB bit is not used if RWBEN = 0.
0 Write cycle will be matched
1 Read cycle will be matched
Note: RWB and RWBEN are not used in full mode.
Table 7-16. Breakpoint Mask Bits for First Address
BKAMBH:BKAMBL
x:0
0:1
1:1
1. If PPAGE is selected.
Address Compare
Full address compare
256 byte address range
16K byte address range
DBGCAX
Yes⁽¹⁾
Yes¹
Yes¹
DBGCAH
Yes
Yes
No
DBGCAL
Yes
No
No
Table 7-17. Breakpoint Mask Bits for Second Address (Dual Mode)
BKBMBH:BKBMBL
x:0
0:1
1:1
1. If PPAGE is selected.
Address Compare
Full address compare
256 byte address range
16K byte address range
DBGCBX
Yes⁽¹⁾
Yes¹
Yes¹
DBGCBH
Yes
Yes
No
DBGCBL
Yes
No
No
Table 7-18. Breakpoint Mask Bits for Data Breakpoints (Full Mode)
BKBMBH:BKBMBL
Data Compare
DBGCBX
0:0
High and low byte compare
No⁽¹⁾
0:1
High byte
No¹
1:0
Low byte
No¹
1:1
No compare
No¹
1. Expansion addresses for breakpoint B are not applicable in this mode.
DBGCBH
Yes
Yes
No
No
DBGCBL
Yes
No
Yes
No
208
MC9S12Q128
Freescale Semiconductor
Rev 1.10