MC9S12Q128_10 Datasheet, PDF (61/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Vector Address
0xFFDA, 0xFFDB
0xFFD8, 0xFFD9
0xFFD6, 0xFFD7
0xFFD4, 0xFFD5
0xFFD2, 0xFFD3
0xFFD0, 0xFFD1
0xFFCE, 0xFFCF
0xFFCC, 0xFFCD
0xFFCA, 0xFFCB
0xFFC8, 0xFFC9
0xFFC6, 0xFFC7
0xFFC4, 0xFFC5
0xFFBA to 0xFFC3
0xFFB8, 0xFFB9
0xFFB6, 0xFFB7
0xFFB4, 0xFFB5
0xFFB2, 0xFFB3
0xFFB0, 0xFFB1
0xFF90 to 0xFFAF
0xFF8E, 0xFF8F
0xFF8C, 0xFF8D
0xFF8A, 0xFF8B
0xFF80 to 0xFF89
Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family)
Table 1-9. Interrupt Vector Locations (continued)
Interrupt Source
Pulse accumulator input edge
SPI
SCI
ATD
Port J
CRG PLL lock
CRG self clock mode
FLASH
CAN wake-up
CAN errors
CAN receive
CAN transmit
Port P
VREG LVI
CCR
Mask
Local Enable
I bit
PACTL (PAI)
I bit
SPICR1 (SPIE, SPTIE)
I bit
SCICR2
(TIE, TCIE, RIE, ILIE)
Reserved
I bit
ATDCTL2 (ASCIE)
Reserved
I bit
PIEP (PIEP7-6)
Reserved
Reserved
Reserved
I bit
PLLCR (LOCKIE)
I bit
PLLCR (SCMIE)
Reserved
I bit
FCNFG (CCIE, CBEIE)
I bit
CANRIER (WUPIE)
I bit CANRIER (CSCIE, OVRIE)
I bit
CANRIER (RXFIE)
I bit
CANTIER (TXEIE[2:0])
Reserved
I bit
Reserved
I bit
Reserved
PIEP (PIEP7-0)
CTRL0 (LVIE)
HPRIO Value
to Elevate
0x00DA
0x00D8
0x00D6
0x00D2
0x00CE
0x00C6
0x00C4
0x00B8
0x00B6
0x00B4
0x00B2
0x00B0
0x008E
0x008A
Freescale Semiconductor
MC9S12Q128
61
Rev 1.10