MC9S12Q128_10 Datasheet, PDF (439/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

15.3.2.6 Timer System Control Register 1 (TSCR1)
Chapter 15 Timer Module (TIM16B6C)
Module Base + 0x0006
7
6
5
4
3
2
1
0
R
0
0
0
0
TEN
TSWAI
TSFRZ
TFFCA
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-12. Timer System Control Register 1 (TSCR1)
Read: Anytime
Write: Anytime
Table 15-6. TSCR1 Field Descriptions
Field
7
TEN
6
TSWAI
5
TSFRZ
4
TFFCA
Description
Timer Enable
0 Disables the main timer, including the counter. Can be used for reducing power consumption.
1 Allows the timer to function normally.
If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator because the ÷64 is
generated by the timer prescaler.
Timer Module Stops While in Wait
0 Allows the timer module to continue running during wait.
1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU
out of wait.
TSWAI also affects pulse accumulator.
Timer Stops While in Freeze Mode
0 Allows the timer counter to continue running while in freeze mode.
1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation.
TSFRZ does not stop the pulse accumulator.
Timer Fast Flag Clear All
0 Allows the timer flag clearing to function normally.
1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010–0x001F)
causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT
register (0x0004, 0x0005) clears the TOF flag. Any access to the PACNT registers (0x0022, 0x0023) clears
the PAOVF and PAIF flags in the PAFLG register (0x0021). This has the advantage of eliminating software
overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to
unintended accesses.
Freescale Semiconductor
MC9S12Q128
439
Rev 1.10