MC9S12Q128_10 Datasheet, PDF (444/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 15 Timer Module (TIM16B6C)
Table 15-14. TSCR2 Field Descriptions
Field
7
TOI
3
TCRE
2
PR[2:0]
Description
Timer Overflow Interrupt Enable
0 Interrupt inhibited.
1 Hardware interrupt requested when TOF flag set.
Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful output compare 7
event. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset inhibited and counter free runs.
1 Counter reset by a successful output compare 7.
Note: If TC7 = 0x0000 and TCRE = 1, TCNT stays at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1, TOF
will never be set when TCNT is reset from 0xFFFF to 0x0000. TCRE=1 and TC7!=0, the TCNT cycle
period is TC7 x "prescaler counter width" + "1 Bus Clock", for a more detailed explanation please refer to
Section 15.4.3, “Output Compare
Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the
Bus Clock as shown in Table 15-15.
Table 15-15. Timer Clock Selection
PR2
PR1
PR0
Timer Clock
0
0
0
Bus Clock / 1
0
0
1
Bus Clock / 2
0
1
0
Bus Clock / 4
0
1
1
Bus Clock / 8
1
0
0
Bus Clock / 16
1
0
1
Bus Clock / 32
1
1
0
Bus Clock / 64
1
1
1
Bus Clock / 128
NOTE
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
444
MC9S12Q128
Freescale Semiconductor
Rev 1.10