MC9S12Q128_10 Datasheet, PDF (40/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family)
Table 1-2. Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued)
Address
Name
0xXXX4– CANxRDSR0–
0xXXXB CANxRDSR7
0xXXXC CANRxDLR
0xXXXD Reserved
0xXXXE CANxRTSRH
0xXXXF CANxRTSRL
0xxx10
Extended ID
CANxTIDR0
Standard ID
0xxx11
Extended ID
CANxTIDR1
Standard ID
0xxx12
Extended ID
CANxTIDR2
Standard ID
0xxx13
Extended ID
CANxTIDR3
Standard ID
0xxx14– CANxTDSR0–
0xxx1B CANxTDSR7
0xxx1C CANxTDLR
0xxx1D CONxTTBPR
0xxx1E CANxTTSRH
0xxx1F CANxTTSRL
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
DB7
TSR15
TSR7
ID28
ID10
ID20
ID2
ID14
ID6
DB7
PRIO7
TSR15
TSR7
Bit 6
DB6
TSR14
TSR6
ID27
ID9
ID19
ID1
ID13
ID5
DB6
PRIO6
TSR14
TSR6
Bit 5
DB5
TSR13
TSR5
ID26
ID8
ID18
ID0
ID12
ID4
DB5
PRIO5
TSR13
TSR5
Bit 4
DB4
Bit 3
DB3
DLC3
TSR12 TSR11
TSR4 TSR3
ID25
ID24
ID7
ID6
SRR=1 IDE=1
RTR
IDE=0
ID11
ID10
ID3
ID2
DB4
DB3
DLC3
PRIO4
TSR12
PRIO3
TSR11
TSR4 TSR3
Bit 2
DB2
DLC2
TSR10
TSR2
ID23
ID5
ID17
ID9
ID1
DB2
DLC2
PRIO2
TSR10
TSR2
Bit 1
DB1
DLC1
TSR9
TSR1
ID22
ID4
ID16
ID8
ID0
DB1
DLC1
PRIO1
TSR9
TSR1
Bit 0
DB0
DLC0
TSR8
TSR0
ID21
ID3
ID15
ID7
RTR
DB0
DLC0
PRIO0
TSR8
TSR0
0x0180–0x023F Reserved
Address
0x0180–
0x023F
Name
Reserved
Read:
Write:
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
40
MC9S12Q128
Freescale Semiconductor
Rev 1.10