MC9S12Q128_10 Datasheet, PDF (356/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description
PCKA2
0
0
0
0
1
1
1
1
Table 12-6. Clock A Prescaler Selects
PCKA1
0
0
1
1
0
0
1
1
PCKA0
0
1
0
1
0
1
0
1
Value of Clock A
Bus Clock
Bus Clock / 2
Bus Clock / 4
Bus Clock / 8
Bus Clock / 16
Bus Clock / 32
Bus Clock / 64
Bus Clock / 128
12.3.2.5 PWM Center Align Enable Register (PWMCAE)
The PWMCAE register contains control bits for the selection of center aligned outputs or left aligned
outputs for each PWM channel. If the CAEx bit is set to a 1, the corresponding PWM output will be center
aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. Reference
Section 12.4.2.5, “Left Aligned Outputs,” and Section 12.4.2.6, “Center Aligned Outputs,” for a more
detailed description of the PWM output modes.
Module Base + 0x0004
7
6
5
4
3
2
1
R
0
0
W
CAE3
CAE2
CAE1
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-7. PWM Center Align Enable Register (PWMCAE)
Read: anytime
Write: anytime
NOTE
Write these bits only when the corresponding channel is disabled.
0
CAE0
0
Field
3
CAE3
2
CAE2
Table 12-7. PWMCAE Field Descriptions
Description
Center Aligned Output Mode on Channel 3
1 Channel 3 operates in left aligned output mode.
1 Channel 3 operates in center aligned output mode.
Center Aligned Output Mode on Channel 2
0 Channel 2 operates in left aligned output mode.
1 Channel 2 operates in center aligned output mode.
356
MC9S12Q128
Freescale Semiconductor
Rev 1.10