MC9S12Q128_10 Datasheet, PDF (357/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Field
1
CAE1
0
CAE0
Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description
Table 12-7. PWMCAE Field Descriptions (continued)
Description
Center Aligned Output Mode on Channel 1
0 Channel 1 operates in left aligned output mode.
1 Channel 1 operates in center aligned output mode.
Center Aligned Output Mode on Channel 0
0 Channel 0 operates in left aligned output mode.
1 Channel 0 operates in center aligned output mode.
12.3.2.6 PWM Control Register (PWMCTL)
The PWMCTL register provides for various control of the PWM module.
Module Base + 0x0005
7
6
5
4
3
2
1
0
R
0
W
0
0
CON23
CON01
PSWAI
PFRZ
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-8. PWM Control Register (PWMCTL)
Read: anytime
Write: anytime
There are control bits for concatenation, each of which is used to concatenate a pair of PWM channels into
one 16-bit channel. When channels 2 and 3 are concatenated, channel 2 registers become the high-order
bytes of the double-byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the
high-order bytes of the double-byte channel.
Reference Section 12.4.2.7, “PWM 16-Bit Functions,” for a more detailed description of the concatenation
PWM function.
NOTE
Change these bits only when both corresponding channels are disabled.
Freescale Semiconductor
MC9S12Q128
357
Rev 1.10