MC9S12Q128_10 Datasheet, PDF (20/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family)
1.1.3 Block Diagram
VSSR
VDDR
VDDX
VSSX
VDD2
VSS2
VDD1
VSS1
BKGD
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
RESET
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
TEST/VPP
Figure 1-1. MC9S12Q128-Family Block Diagram
Voltage Regulator
32K, 64K, 96K, 128K Byte Flash/ROM
1K, 2K, 3K, 4K Byte RAM
Single-wire Background
Debug12 Module
HCS12
CPU
PLL
Clock and
Reset
Generation
Module
COP Watchdog
Clock Monitor
Periodic Interrupt
XIRQ
IRQ
R/W
LSTRB/TAGLO
ECLK
MODA/IPIPE0
MODB/IPIPE1
NOACC/XCLKS
System
Integration
Module
(SIM)
ATD
VDDA
VSSA
VRH
VRL
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Timer
Module
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
MUX
PWM
Module
PW0
PW1
PW2
PW3
PWM Module is only available on the
128K and 96K Versions
Multiplexed Address/Data Bus
DDRA
PTA
DDRB
PTB
SCI
RXD
TXD
MSCAN
SPI
RXCAN
TXCAN
MISO
SS
MOSI
SCK
VDDA
VSSA
VRH
VRL
PAD0
PAD1
PAD2
PAD3
PAD4
PAD5
PAD6
PAD7
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PJ6
PJ7
PS0
PS1
PS2
PS3
PM0
PM1
PM2
PM3
PM4
PM5
Multiplexed
Wide Bus
Internal Logic 2.5V
VDD1,2
VSS1,2
I/O Driver 5V
VDDX
VSSX
Signals shown in Bold are not available on the 52 or 48 Pin Package
Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package
PLL 2.5V
VDDPLL
VSSPLL
A/D Converter 5V
VDDA
VSSA
VRL is bonded internally to VSSA
for 52 and 48 Pin packages
Voltage Regulator 5V & I/O
VDDR
VSSR
20
MC9S12Q128
Freescale Semiconductor
Rev 1.10