MC9S12Q128_10 Datasheet, PDF (107/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Port
T
S
M
P
J
A
B
E
Chapter 2 Port Integration Module (PIM9C32) Block Description
Table 2-39. Port Reset State Summary
Data Direction
Input
Input
Input
Input
Input
Pull Mode
Hi-z
Pull up
Pull up
Hi-z
Hi-z
Reset States
Reduced Drive
Disabled
Disabled
Disabled
Disabled
Disabled
Wired-OR Mode
n/a
Disabled
Disabled
n/a
n/a
Interrupt
n/a
n/a
n/a
Disabled
Disabled
Refer to MEBI Block Guide for details.
BKGD pin
Refer to BDM Block Guide for details.
2.6 Interrupts
Port P and J generate a separate edge sensitive interrupt if enabled.
2.6.1
Interrupt Sources
Table 2-40. Port Integration Module Interrupt Sources
Interrupt Source
Port P
Port J
Interrupt Flag
PIFP[7:0]
PIFJ[7:6]
Local Enable
PIEP[7:0]
PIEJ[7:6]
Global (CCR) Mask
I Bit
I Bit
NOTE
Vector addresses and their relative interrupt priority are determined at the
MCU level.
2.6.2 Recovery from STOP
The PIM can generate wake-up interrupts from STOP on port P and J. For other sources of external
interrupts please refer to the respective Block User Guide.
2.7 Application Information
It is not recommended to write PORTx and DDRx in a word access. When changing the register pins from
inputs to outputs, the data may have extra transitions during the write access. Initialize the port data register
before enabling the outputs.
Power consumption will increase the more the voltages on general purpose input pins deviate from the
supply voltages towards mid-range because the digital input buffers operate in the linear region.
Freescale Semiconductor
MC9S12Q128
107
Rev 1.10