MC9S12Q128_10 Datasheet, PDF (436/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 15 Timer Module (TIM16B6C)
Address Name
Bit 7
6
5
4
3
2
0x0010–
0x0013
Reserved
R
W
R
0x0014– TCxH– ^W
0x001F TCxL _R
W
Bit 15
Bit 7
Bit 14
Bit 6
Bit 13
Bit 5
Bit 12
Bit 4
Bit 11
Bit 3
Bit 10
Bit 2
0x0020
0x0021
0x0022
R
0
PACTL
W
R
0
PAFLG
W
R
PACNTH
PACNT15
W
PAEN
0
PACNT14
PAMOD
0
PACNT13
PEDGE
0
PACNT12
CLK1
0
PACNT11
CLK0
0
PACNT10
R
0x0023 PACNTL
W
0x0024–
0x002F
Reserved
R
W
PACNT7
PACNT6
PACNT5
PACNT4
PACNT3
PACNT2
1
Bit 9
Bit 1
PAOVI
PAOVF
PACNT9
PACNT1
Bit 0
Bit 8
Bit 0
PAI
PAIF
PACNT8
PACNT0
= Unimplemented or Reserved
Figure 15-5. TIM16B6C Register Summary (continued)
15.3.2.1 Timer Input Capture/Output Compare Select (TIOS)
Module Base + 0x0000
7
6
5
4
3
2
1
0
R
IOS7
W
IOS6
IOS5
IOS4
IOS3
IOS2
Reset
0
0
0
0
0
0
0
0
Figure 15-6. Timer Input Capture/Output Compare Select (TIOS)
Read: Anytime
Write: Anytime
Table 15-2. TIOS Field Descriptions
Field
7:2
IOS[7:2]
Description
Input Capture or Output Compare Channel Configuration
0 The corresponding channel acts as an input capture.
1 The corresponding channel acts as an output compare.
436
MC9S12Q128
Freescale Semiconductor
Rev 1.10