MC9S12Q128_10 Datasheet, PDF (275/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Core req’s
Wait Mode.
PLLWAI=1 ^no
?
yes
Clear
PLLSEL,
Disable PLL
CWAI or
SYSWAI=1
?
yes
Disable
core clocks
no
SYSWAI=1 ^no
?
yes
Disable
system clocks
Enter
Wait Mode
Wait Mode left
due to external
reset
Exit Wait w.
ext.RESET
CME=1 ^no
?
yes
CM fail
no
?
yes
Exit Wait w. no
CMRESET
SCME=1
?
yes
Generate
SCM Interrupt
(Wakeup from Wait)
SCMIE=1 ^no
?
yes
Exit
Wait Mode
no
INT
?
yes
Exit
Wait Mode
SCM=1 ^no
?
yes
Enter
Enter
SCM
SCM
Continue w.
normal OP
Figure 9-23. Wait Mode Entry/Exit Sequence
Freescale Semiconductor
MC9S12Q128
275
Rev 1.10