MC9S12Q128_10 Datasheet, PDF (377/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description
12.4.2.8 PWM Boundary Cases
Table 12-12 summarizes the boundary conditions for the PWM regardless of the output mode (left aligned
or center aligned) and 8-bit (normal) or 16-bit (concatenation):
Table 12-12. PWM Boundary Cases
PWMDTYx
PWMPERx
0x0000
(indicates no duty)
>0x0000
0x0000
(indicates no duty)
XX
XX
>0x0000
0x0000⁽¹⁾
(indicates no period)
0x0000¹
(indicates no period)
>= PWMPERx
XX
>= PWMPERx
XX
1. Counter = 0x0000 and does not count.
PPOLx
1
0
1
0
1
0
PWMx Output
Always Low
Always High
Always High
Always Low
Always High
Always Low
12.5 Resets
The reset state of each individual bit is listed within the register description section (see Section 12.3,
“Memory Map and Registers,” which details the registers and their bit-fields. All special functions or
modes which are initialized during or just following reset are described within this section.
• The 8-bit up/down counter is configured as an up counter out of reset.
• All the channels are disabled and all the counters don’t count.
12.6 Interrupts
The PWM8B4C module interrupt is disabled when PWM5ENA is clear.
CAUTION
User Software must ensure that PWM5ENA remains clear
A description of the registers involved and affected due to this interrupt is explained in Section 12.3.2.15,
“PWM Shutdown Register (PWMSDN).”
Freescale Semiconductor
MC9S12Q128
377
Rev 1.10