MC9S12Q128_10 Datasheet, PDF (354/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description
12.3.2.3 PWM Clock Select Register (PWMCLK)
Each PWM channel has a choice of two clocks to use as the clock source for that channel as described
below.
Module Base + 0x0002
7
6
5
4
3
2
1
R
0
0
W
PCLK3
PCLK2
PCLK1
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-5. PWM Clock Select Register (PWMCLK)
Read: anytime
Write: anytime
NOTE
Register bits PCLK0 to PCLK3 can be written anytime. If a clock select is
changed while a PWM signal is being generated, a truncated or stretched
pulse can occur during the transition.
0
PCLK0
0
Field
3
PCLK3
2
PCLK2
1
PCLK1
0
PCLK0
Table 12-3. PWMCLK Field Descriptions
Description
Pulse Width Channel 3 Clock Select
0 Clock B is the clock source for PWM channel 3.
1 Clock SB is the clock source for PWM channel 3.
Pulse Width Channel 2 Clock Select
0 Clock B is the clock source for PWM channel 2.
1 Clock SB is the clock source for PWM channel 2.
Pulse Width Channel 1 Clock Select
0 Clock A is the clock source for PWM channel 1.
1 Clock SA is the clock source for PWM channel 1.
Pulse Width Channel 0 Clock Select
0 Clock A is the clock source for PWM channel 0.
1 Clock SA is the clock source for PWM channel 0.
354
MC9S12Q128
Freescale Semiconductor
Rev 1.10