MC9S12Q128_10 Datasheet, PDF (100/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2.6 Port AD Registers
2.3.2.6.1 Port AD I/O Register (PTAD)
Module Base + 0x0030
R
W
Reset
7
PTAD7
0
6
PTAD6
5
PTAD5
4
PTAD4
3
PTAD3
2
PTAD2
0
0
0
0
0
Figure 2-40. Port AD I/O Register (PTAD)
1
PTAD1
0
0
PTAD0
0
Read: Anytime.
Write: Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
2.3.2.6.2 Port AD Input Register (PTIAD)
Module Base + 0x0031
R
W
Reset
7
PTIAD7
—
6
PTIAD6
5
PTIAD5
4
PTIAD4
3
PTIAD3
2
PTIAD2
—
—
—
—
—
= Unimplemented or Reserved
Figure 2-41. Port AD Input Register (PTIAD)
1
PTIAD1
—
0
PTIAD0
—
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins. This can be used to detect overload or
short circuit conditions on output pins.
100
MC9S12Q128
Freescale Semiconductor
Rev 1.10