MC9S12Q128_10 Datasheet, PDF (351/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description
Address Name
Bit 7
6
5
4
3
2
1
Bit 0
R
0x0013 PWMPER1
Bit 7
6
5
4
3
2
1
Bit 0
W
R
0x0014 PWMPER2
Bit 7
6
5
4
3
2
1
Bit 0
W
R
0x0015 PWMPER3
Bit 7
6
5
4
3
2
1
Bit 0
W
R
0x0016 Reserved
W
R
0x0017 Reserved
W
R
0x0018 PWMDTY0
Bit 7
6
5
4
3
2
1
Bit 0
W
R
0x0019 PWMPER1
Bit 7
6
5
4
3
2
1
Bit 0
W
R
0x001A PWMPER2
Bit 7
6
5
4
3
2
1
Bit 0
W
R
0x001B PWMPER3
Bit 7
6
5
4
3
2
1
Bit 0
W
R
0x001C Reserved
W
R
0x001D Reserved
W
R
0
0
PWM5IN
0x001E PWMSDB
PWMIF PWMIE
PWMLVL
PWM5INL PWM5ENA
W
PWMRSTRT
= Unimplemented or Reserved
Figure 12-2. PWM Register Summary (continued)
12.3.2.1 PWM Enable Register (PWME)
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx
bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM
waveform is not available on the associated PWM output until its clock source begins its next cycle due to
the synchronization of PWMEx and the clock source.
NOTE
The first PWM cycle after enabling the channel can be irregular.
An exception to this is when channels are concatenated. After concatenated mode is enabled (CONxx bits
set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the
low-order PWMEx bit. In this case, the high-order bytes PWMEx bits have no effect and their
corresponding PWM output lines are disabled.
While in run mode, if all PWM channels are disabled (PWME3–PWME0 = 0), the prescaler counter shuts
off for power savings.
Freescale Semiconductor
MC9S12Q128
351
Rev 1.10