MC9S12Q128_10 Datasheet, PDF (50/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family)
1.3.4 Detailed Signal Descriptions
1.3.4.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
1.3.4.2 RESET — External Reset Pin
RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known
start-up state. It also acts as an open-drain output to indicate that an internal failure has been detected in
either the clock monitor or COP watchdog circuit. External circuitry connected to the RESET pin should
not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one
within 32 ECLK cycles after the low drive is released. Upon detection of any reset, an internal circuit
drives the RESET pin low and a clocked reset sequence controls when the MCU can begin normal
processing.
1.3.4.3 TEST / V_PP — Test Pin
This pin is reserved for test and must be tied to V_SS in all applications.
1.3.4.4 XFC — PLL Loop Filter Pin
Dedicated pin used to create the PLL loop filter. See CRG BUG for more detailed information.PLL loop
filter. Please ask your Motorola representative for the interactive application note to compute PLL loop
filter elements. Any current leakage on this pin must be avoided.
XFC
MCU
R₀
C_P
C_S
V_DDPLL
V_DDPLL
Figure 1-9. PLL Loop Filter Connections
1.3.4.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin
The BKGD / TAGHI / MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is also used as a MCU operating mode select pin at the rising edge during reset, when
the state of this pin is latched to the MODC bit.
50
MC9S12Q128
Freescale Semiconductor
Rev 1.10