MC9S12Q128_10 Datasheet, PDF (375/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description
To calculate the output frequency in center aligned output mode for a particular channel, take the selected
clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period
register for that channel.
• PWMx frequency = clock (A, B, SA, or SB) / (2*PWMPERx)
• PWMx duty cycle (high time as a% of period):
— Polarity = 0 (PPOLx = 0)
Duty cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
— Polarity = 1 (PPOLx = 1)
Duty cycle = [PWMDTYx / PWMPERx] * 100%
As an example of a center aligned output, consider the following case:
Clock source = bus clock, where bus clock = 10 MHz (100 ns period)
PPOLx = 0
PWMPERx = 4
PWMDTYx = 1
PWMx frequency = 10 MHz/8 = 1.25 MHz
PWMx period = 800 ns
PWMx duty cycle = 3/4 *100% = 75%
Shown below is the output waveform generated.
E = 100 ns
E = 100 ns
DUTY CYCLE = 75%
PERIOD = 800 ns
Figure 12-33. PWM Center Aligned Output Example Waveform
12.4.2.7 PWM 16-Bit Functions
The PWM timer also has the option of generating 4-channels of 8-bits or 2-channels of 16-bits for greater
PWM resolution}. This 16-bit channel option is achieved through the concatenation of two 8-bit channels.
The PWMCTL register contains three control bits, each of which is used to concatenate a pair of PWM
channels into one 16-bit channel. Channels 2 and 3 are concatenated with the CON23 bit, and channels 0
and 1 are concatenated with the CON01 bit.
NOTE
Change these bits only when both corresponding channels are disabled.
When channels 2 and 3 are concatenated, channel 2 registers become the high-order bytes of the double
byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high-order bytes
of the double byte channel.
Freescale Semiconductor
MC9S12Q128
375
Rev 1.10