MC9S12Q128_10 Datasheet, PDF (273/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
If the PRE bit is set, the RTI will continue to run in pseudo-stop mode.
.
WAIT(RTIWAI),
STOP(PSTP,PRE),
RTI enable
OSCCLK
÷ 1024
RTR[6:4]
0:0:0
0:0:1
÷2
0:1:0
÷2
0:1:1
÷2
1:0:0
÷2
1:0:1
gating condition
= Clock Gate
÷2
1:1:0
÷2
1:1:1
4-BIT MODULUS
RTI TIMEOUT
COUNTER (RTR[3:0])
Figure 9-22. Clock Chain for RTI
9.4.7 Modes of Operation
9.4.7.1 Normal Mode
The CRGV4 block behaves as described within this specification in all normal modes.
9.4.7.2 Self-Clock Mode
The VCO has a minimum operating frequency, f_SCM. If the external clock frequency is not available due
to a failure or due to long crystal start-up time, the bus clock and the core clock are derived from the VCO
running at minimum operating frequency; this mode of operation is called self-clock mode. This requires
CME = 1 and SCME = 1. If the MCU was clocked by the PLL clock prior to entering self-clock mode, the
PLLSEL bit will be cleared. If the external clock signal has stabilized again, the CRG will automatically
select OSCCLK to be the system clock and return to normal mode. See Section 9.4.4, “Clock Quality
Checker” for more information on entering and leaving self-clock mode.
Freescale Semiconductor
MC9S12Q128
273
Rev 1.10