MC9S12Q128_10 Datasheet, PDF (628/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Appendix A Electrical Characteristics
In Figure A-9 the timing diagram for slave mode with transmission format CPHA=1 is depicted.
SS
(INPUT)
SCK
(CPOL = 0)
(INPUT)
SCK
(CPOL = 1)
(INPUT)
MISO
(OUTPUT)
1
2
4
4
9
see
note
SLAVE
MSB OUT
MOSI
(INPUT)
7
5
6
MSB IN
NOTE: Not defined!
12
12
11
BIT 6 . . . 1
BIT 6 . . . 1
3
13
13
8
SLAVE LSB OUT
LSB IN
Figure A-9. SPI Slave Timing (CPHA=1)
In Table A-22 the timing characteristics for slave mode are listed.
Table A-22. SPI Slave Mode Timing Characteristics
Num
1
1
2
3
4
5
6
7
8
9
C
Characteristic
D SCK Frequency
P SCK Period
D Enable Lead Time
D Enable Lag Time
D Clock (SCK) High or Low Time
D Data Setup Time (Inputs)
D Data Hold Time (Inputs)
D Slave Access Time (time to data active)
D Slave MISO Disable Time
D ^{Data Valid after SCK Edge}
10
D Data Valid after SS fall
11
D Data Hold Time (Outputs)
12
D Rise and Fall Time Inputs
13
D Rise and Fall Time Outputs
1. t_bus added due to internal synchronization delay
Symbol Min
f_sck
DC
t_sck
4
t_lead
4
t_lag
4
t_wsck
4
t_su
8
t_hi
8
t_a
—
t_dis
—
t_vsck
—
t_vss
—
t_ho
20
t_rfi
—
t_rfo
—
Typ
Max
Unit
—
1/4
f_bus
—
∞
t_bus
—
—
t_bus
—
—
t_bus
—
—
t_bus
—
—
ns
—
—
ns
—
20
ns
—
22
ns
—
30 + t_bus
(1)
ns
—
30 + t_bus1
ns
—
—
ns
—
8
ns
—
8
ns
628
MC9S12Q128
Freescale Semiconductor
Rev 1.10