MC9S12Q128_10 Datasheet, PDF (355/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description
12.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK)
This register selects the prescale clock source for clocks A and B independently.
Module Base + 0x0003
7
R
0
W
Reset
0
Read: anytime
6
5
4
3
2
1
0
PCKB2
PCKB1
PCKB0
PCKA2
PCKA1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-6. PWM Prescaler Clock Select Register (PWMPRCLK)
Write: anytime
NOTE
PCKB2–PCKB0 and PCKA2–PCKA0 register bits can be written anytime.
If the clock prescale is changed while a PWM signal is being generated, a
truncated or stretched pulse can occur during the transition.
0
PCKA0
0
Table 12-4. PWMPRCLK Field Descriptions
Field
Description
6–5
Prescaler Select for Clock B — Clock B is 1 of two clock sources which can be used for channels 2 or 3. These
PCKB[2:0] three bits determine the rate of clock B, as shown in Table 12-5.
2–0
Prescaler Select for Clock A — Clock A is 1 of two clock sources which can be used for channels 0, 1, 4, or 5.
PCKA[2:0] These three bits determine the rate of clock A, as shown in Table 12-6.
PCKB2
0
0
0
0
1
1
1
1
Table 12-5. Clock B Prescaler Selects
PCKB1
0
0
1
1
0
0
1
1
PCKB0
0
1
0
1
0
1
0
1
Value of Clock B
Bus Clock
Bus Clock / 2
Bus Clock / 4
Bus Clock / 8
Bus Clock / 16
Bus Clock / 32
Bus Clock / 64
Bus Clock / 128
Freescale Semiconductor
MC9S12Q128
355
Rev 1.10