MC9S12Q128_10 Datasheet, PDF (88/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2.3 Port M Registers
2.3.2.3.1 Port M I/O Register (PTM)
Module Base + 0x0010
7
R
0
W
6
5
4
3
2
0
PTM5
PTM4
PTM3
PTM2
MSCAN/
SPI
—
—
SCK
MOSI
SS
MISO
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-17. Port M I/O Register (PTM)
1
PTM1
0
PTM0
TXCAN
0
RXCAN
0
Read: Anytime.
Write: Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
The SPI pin configurations (PM[5:2]) is determined by several status bits in the SPI module. Please refer
to the SPI Block User Guide for details.
2.3.2.3.2 Port M Input Register (PTIM)
Module Base + 0x0011
7
R
0
6
5
4
3
2
0
PTIM5
PTIM4
PTIM3
PTIM2
W
Reset
—
—
—
—
—
—
= Unimplemented or Reserved
Figure 2-18. Port M Input Register (PTIM)
1
PTIM1
—
0
PTIM0
—
Read: Anytime.
Write: Never, writes to this register have no effect.
Table 2-16. PTIM Field Descriptions
Field
Description
5–0
Port M Input Register — This register always reads back the status of the associated pins. This also can be
PTIM[5:0] used to detect overload or short circuit conditions on output pins.
88
MC9S12Q128
Freescale Semiconductor
Rev 1.10