MC9S12Q128_10 Datasheet, PDF (60/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family)
1.5.3.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU signals (address and data bus) will be fully static. All peripherals stay
active. For further power consumption reduction the peripherals can individually turn off their local clocks.
1.5.3.4 Run
Although this is not a low-power mode, unused peripheral modules should not be enabled in order to save
power.
1.6 Resets and Interrupts
Consult the Exception Processing section of the CPU12 Reference Manual for information.
1.6.1 Vectors
Table 1-9 lists interrupt sources and vectors in default order of priority.
Table 1-9. Interrupt Vector Locations
Vector Address
0xFFFE, 0xFFFF
0xFFFC, 0xFFFD
0xFFFA, 0xFFFB
0xFFF8, 0xFFF9
0xFFF6, 0xFFF7
0xFFF4, 0xFFF5
0xFFF2, 0xFFF3
0xFFF0, 0xFFF1
$FFEE, $FFEF
$FFEC, $FFED
0xFFEA, 0xFFEB
0xFFE8, 0xFFE9
0xFFE6, 0xFFE7
0xFFE4, 0xFFE5
0xFFE2, 0xFFE3
0xFFE0, 0xFFE1
0xFFDE, 0xFFDF
0xFFDC, 0xFFDD
Interrupt Source
External reset, power on reset,
or low voltage reset
(see CRG flags register to determine
reset source)
Clock monitor fail reset
COP failure reset
Unimplemented instruction trap
SWI
XIRQ
IRQ
Real time Interrupt
Standard timer channel 2
Standard timer channel 3
Standard timer channel 4
Standard timer channel 5
Standard timer channel 6
Standard timer channel 7
Standard timer overflow
Pulse accumulator A overflow
CCR
Mask
Local Enable
None
None
None COPCTL (CME, FCME)
None
COP rate select
None
None
None
None
X-Bit
None
I bit
INTCR (IRQEN)
I bit
CRGINT (RTIE)
Reserved
Reserved
I bit
TIE (C2I)
I bit
TIE (C3I)
I bit
TIE (C4I)
I bit
TIE (C5I)
I bit
TIE (C6I)
I bit
TIE (C7I)
I bit
TMSK2 (TOI)
I bit
PACTL (PAOVI)
HPRIO Value
to Elevate
—
—
—
—
—
—
0x00F2
0x00F0
0x00EA
0x00E8
0x00E6
0x00E4
0x00E2
0x00E0
0x00DE
0x00DC
60
MC9S12Q128
Freescale Semiconductor
Rev 1.10