MC9S12Q128_10 Datasheet, PDF (49/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family)
Table 1-5. Signal Properties (continued)
Pin Name Pin Name Pin Name Power
Function 1 Function 2 Function 3 Domain
Internal Pull
Resistor
CTRL
Reset
State
Description
PP[2:0]
KWP[2:0]
PW[2:0]
V_DDX
PERP/
PPSP
Disabled ^{Port P I/O pins, keypad wake-up, PWM outputs}
PJ[7:6]
KWJ[7:6]
—
V_DDX
PERJ/
PPSJ
Disabled ^{Port J I/O pins and keypad wake-up}
PM5
SCK
—
V_DDX
PERM/
PPSM
Up ^{Port M I/O pin and SPI SCK signal}
PM4
MOSI
—
V_DDX
PERM/
PPSM
Up ^{Port M I/O pin and SPI MOSI signal}
PM3
SS
—
V_DDX
PERM/
PPSM
Up ^{Port M I/O pin and SPI SS signal}
PM2
MISO
—
V_DDX
PERM/
PPSM
Up ^{Port M I/O pin and SPI MISO signal}
PM1
TXCAN
—
V_DDX
PERM/
PPSM
Up ^{Port M I/O pin and CAN transmit signal}
PM0
RXCAN
—
V_DDX
PERM/
PPSM
Up ^{Port M I/O pin and CAN receive signal}
PS[3:2]
—
—
V_DDX
PERS/
PPSS
Up ^{Port S I/O pins}
PS1
TXD
—
V_DDX
PERS/
PPSS
Up ^{Port S I/O pin and SCI transmit signal}
PS0
RXD
—
V_DDX
PERS/
PPSS
Up ^{Port S I/O pin and SCI receive signal}
PT[7:5]
IOC[7:5]
—
V_DDX
PERT/
PPST
Disabled ^{Port T I/O pins shared with timer (TIM)}
PT[4:0]
IOC[4:2]
PW[3:0]
V_DDX
PERT/
PPST
Disabled ^{Port T I/O pins shared with timer and PWM}
1. The Port E output buffer enable signal control at reset is determined by the PEAR register and is mode dependent. For
example, in special test mode RDWE = LSTRE = 1 which enables the PE[3:2] output buffers and disables the pull-ups. Refer
to S12_MEBI user guide for PEAR register details.
1.3.3 Pin Initialization for 48- and 52-Pin LQFP Bond Out Versions
Not Bonded Pins:
If the port pins are not bonded out in the chosen package the user should initialize the registers to
be inputs with enabled pull resistance to avoid excess current consumption. This applies to the
following pins:
(48LQFP): Port A[7:1], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[4:0], Port
J[7:6], PortS[3:2]
(52LQFP): Port A[7:3], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[2:0], Port
J[7:6], PortS[3:2]
Freescale Semiconductor
MC9S12Q128
49
Rev 1.10