MC9S12Q128_10 Datasheet, PDF (445/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

15.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Chapter 15 Timer Module (TIM16B6C)
Module Base + 0x000E
7
6
5
4
3
2
1
0
R
C7F
C6F
C5F
C4F
C3F
C2F
W
Reset
0
0
0
0
0
0
0
0
Figure 15-20. Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero
will not affect current status of the bit.
Table 15-16. TRLG1 Field Descriptions
Field
7:2
C[7:2]F
Description
Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output
compare event occurs. Clear a channel flag by writing one to it.
When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel
(0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared.
15.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
Module Base + 0x000F
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
TOF
W
Reset
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 15-21. Main Timer Interrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit
to one.
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
Table 15-17. TRLG2 Field Descriptions
Field
7
TOF
Description
Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. This bit is cleared
automatically by a write to the TFLG2 register with bit 7 set. (See also TCRE control bit explanation.)
Freescale Semiconductor
MC9S12Q128
445
Rev 1.10