MC9S12Q128_10 Datasheet, PDF (63/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family)
Device
MC9S12Q32
MC9S12Q64
MC9S12Q96
MC9S12Q128
PAGE
3E
3F
3C
3D
3E
3F
3A
3B
3C
3D
3E
3F
38
39
3A
3B
3C
3D
3E
3F
Table 1-11. Device Specific Flash PAGE Mapping
PAGE Visible with PPAGE Contents
$00,$02,$04,$06,$08,$0A,$0C,$0E,$10,$12......$2C,$2E,$30,$32,$34,$36,$38,$3A,$3C,$3E
$01,$03,$05,$07,$09,$0B,$0D,$0F,$11,$13.....$2D,$2F,$31,$33,$35,$37,$39,$3B,$3D,$3F
$04,$0C,$14,$1C,$24,$2C,$34,$3C
$05,$0D,$15,$1D,$25,$2D,$35,$3D
$06,$0E,$16,$1E,$26,$2E,$36,$3E
$07,$0F,$17,$1F,$27,$2F,$37,$3F
$02,$0A,$12,$1A,$22,$2A,$32,$3A
$03,$0B,$13,$1B,$23,$2B,$33,$3B
$04,$0C,$14,$1C,$24,$2C,$34,$3C
$05,$0D,$15,$1D,$25,$2D,$35,$3D
$06,$0E,$16,$1E,$26,$2E,$36,$3E
$07,$0F,$17,$1F,$27,$2F,$37,$3F
$00,$08,$10,$18,$20,$28,$30,$38
$01,$09,$11,$19,$21,$29,$31,$39
$02,$0A,$12,$1A,$22,$2A,$32,$3A
$03,$0B,$13,$1B,$23,$2B,$33,$3B
$04,$0C,$14,$1C,$24,$2C,$34,$3C
$05,$0D,$15,$1D,$25,$2D,$35,$3D
$06,$0E,$16,$1E,$26,$2E,$36,$3E
$07,$0F,$17,$1F,$27,$2F,$37,$3F
1.7.2 BDM Alternate Clock
The BDM section reference to alternate clock is equivalent to the oscillator clock.
1.7.3 Extended Address Range Emulation Implications
In order to emulate the devices, external addressing of a 128K memory map is required. This is provided
in a 112 LQFP package version which includes the 3 necessary extra external address bus signals via
PortK[2:0]. This package version is for emulation only and not provided as a general production package.
The reset state of DDRK is 0x0000, configuring the pins as inputs.
The reset state of PUPKE in the PUCR register is “1” enabling the internal Port K pullups.
In this reset state the pull-ups provide a defined state and prevent a floating input, thereby preventing
unnecessary current flow at the input stage.
To prevent unnecessary current flow in production package options, the states of DDRK and PUPKE
should not be changed by software.
Freescale Semiconductor
MC9S12Q128
63
Rev 1.10