MC9S12Q128_10 Datasheet, PDF (449/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 15 Timer Module (TIM16B6C)
Field
1
PAOVF
0
PAIF
Table 15-21. PAFLG Field Descriptions
Description
Pulse Accumulator Overflow Flag — Set when the 16-bit pulse accumulator overflows from 0xFFFF to 0x0000.
This bit is cleared automatically by a write to the PAFLG register with bit 1 set.
Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IOC7 input pin.In event
mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at
the IOC7 input pin triggers PAIF.
This bit is cleared by a write to the PAFLG register with bit 0 set.
Any access to the PACNT register will clear all the flags in this register when TFFCA bit in register TSCR(0x0006)
is set.
15.3.2.17 Pulse Accumulators Count Registers (PACNT)
Module Base + 0x0022
15
R
PACNT15
W
14
PACNT14
13
PACNT13
12
PACNT12
11
PACNT11
10
PACNT10
9
PACNT9
Reset
0
0
0
0
0
0
0
Figure 15-26. Pulse Accumulator Count Register High (PACNTH)
0
PACNT8
0
Module Base + 0x0023
R
W
Reset
7
PACNT7
0
6
PACNT6
5
PACNT5
4
PACNT4
3
PACNT3
2
PACNT2
1
PACNT1
0
0
0
0
0
0
Figure 15-27. Pulse Accumulator Count Register Low (PACNTL)
0
PACNT0
0
Read: Anytime
Write: Anytime
These registers contain the number of active input edges on its input pin since the last reset.
When PACNT overflows from 0xFFFF to 0x0000, the Interrupt flag PAOVF in PAFLG (0x0021) is set.
Full count register access should take place in one clock cycle. A separate read/write for high byte and low
byte will give a different result than accessing them as a word.
NOTE
Reading the pulse accumulator counter registers immediately after an active
edge on the pulse accumulator input pin may miss the last count because the
input has to be synchronized with the bus clock first.
Freescale Semiconductor
MC9S12Q128
449
Rev 1.10