MC9S12Q128_10 Datasheet, PDF (437/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

15.3.2.2 Timer Compare Force Register (CFORC)
Chapter 15 Timer Module (TIM16B6C)
Module Base + 0x0001
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W FOC7
FOC6
FOC5
FOC4
FOC3
FOC2
Reset
0
0
0
0
0
0
0
0
Figure 15-7. Timer Compare Force Register (CFORC)
Read: Anytime but will always return 0x0000 (1 state is transient)
Write: Anytime
Table 15-3. CFORC Field Descriptions
Field
Description
7:2
FOC[7:2]
Force Output Compare Action for Channel 7:2— A write to this register with the corresponding data bit(s) set
causes the action which is programmed for output compare “x” to occur immediately. The action taken is the
same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not
get set.
Note: A successful channel 7 output compare overrides any channel 6:2 compares. If forced output compare on
any channel occurs at the same time as the successful output compare then forced output compare action
will take precedence and interrupt flag won’t get set.
15.3.2.3 Output Compare 7 Mask Register (OC7M)
Module Base + 0x0002
7
6
5
4
3
2
1
0
R
OC7M7
W
OC7M6
OC7M5
OC7M4
OC7M3
OC7M2
Reset
0
0
0
0
0
0
0
0
Figure 15-8. Output Compare 7 Mask Register (OC7M)
Read: Anytime
Write: Anytime
Table 15-4. OC7M Field Descriptions
Field
Description
7:2
OC7M[7:2]
Output Compare 7 Mask — Setting the OC7Mx (x ranges from 2 to 6) will set the corresponding port to be an
output port when the corresponding TIOSx (x ranges from 2 to 6) bit is set to be an output compare.
Note: A successful channel 7 output compare overrides any channel 6:2 compares. For each OC7M bit that is
set, the output compare action reflects the corresponding OC7D bit.
Freescale Semiconductor
MC9S12Q128
437
Rev 1.10