MC9S12Q128_10 Datasheet, PDF (443/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

15.3.2.10 Timer Interrupt Enable Register (TIE)
Chapter 15 Timer Module (TIM16B6C)
Module Base + 0x000C
7
6
5
4
3
2
1
0
R
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
W
Reset
0
0
0
0
0
0
0
0
Figure 15-18. Timer Interrupt Enable Register (TIE)
Read: Anytime
Write: Anytime.
CAUTION
User software must ensure that C1I and C0I remain clear.
Table 15-13. TIE Field Descriptions
Field
7:0
C7I:C0I
Description
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
15.3.2.11 Timer System Control Register 2 (TSCR2)
Module Base + 0x000D
7
6
5
4
3
2
1
0
R
0
0
0
TOI
TCRE
PR2
PR1
PR0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-19. Timer System Control Register 2 (TSCR2)
Read: Anytime
Write: Anytime.
Freescale Semiconductor
MC9S12Q128
443
Rev 1.10