MC9S12Q128_10 Datasheet, PDF (452/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 15 Timer Module (TIM16B6C)
Note: in Figure 15-29,if PR[2:0] is equal to 0, one prescaler counter equal to one bus clock
Figure 15-29. The TCNT cycle diagram under TCRE=1 condition
prescaler
counter
1 bus
clock
TC7
0
1
-----
TC7-1
TC7
0
TC7 event
TC7 event
15.4.4 Pulse Accumulator
The pulse accumulator (PACNT) is a 16-bit counter that can operate in two modes:
Event counter mode — Counting edges of selected polarity on the pulse accumulator input pin, PAI.
Gated time accumulation mode — Counting pulses from a divide-by-64 clock. The PAMOD bit selects the
mode of operation.
The minimum pulse width for the PAI input is greater than two bus clocks.
15.4.5 Event Counter Mode
Clearing the PAMOD bit configures the PACNT for event counter operation. An active edge on the IOC7
pin increments the pulse accumulator counter. The PEDGE bit selects falling edges or rising edges to
increment the count.
NOTE
The PACNT input and timer channel 7 use the same pin IOC7. To use the
IOC7, disconnect it from the output logic by clearing the channel 7 output
mode and output level bits, OM7 and OL7. Also clear the channel 7 output
compare 7 mask bit, OC7M7.
The Pulse Accumulator counter register reflect the number of active input edges on the PACNT input pin
since the last reset.
The PAOVF bit is set when the accumulator rolls over from 0xFFFF to 0x0000. The pulse accumulator
overflow interrupt enable bit, PAOVI, enables the PAOVF flag to generate interrupt requests.
NOTE
The pulse accumulator counter can operate in event counter mode even
when the timer enable bit, TEN, is clear.
452
MC9S12Q128
Freescale Semiconductor
Rev 1.10