MC9S12Q128_10 Datasheet, PDF (159/644 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 5 Interrupt (INTV1) Block Description
5.2 External Signal Description
Most interfacing with the interrupt sub-block is done within the core. However, the interrupt does receive
direct input from the multiplexed external bus interface (MEBI) sub-block of the core for the IRQ and
XIRQ pin data.
5.3 Memory Map and Register Definition
Detailed descriptions of the registers and associated bits are given in the subsections that follow.
5.3.1 Module Memory Map
Table 5-1. INT Memory Map
Address
Offset
0x0015
0x0016
0x001F
Use
Interrupt Test Control Register (ITCR)
Interrupt Test Registers (ITEST)
Highest Priority Interrupt (Optional) (HPRIO)
Access
R/W
R/W
R/W
5.3.2 Register Descriptions
5.3.2.1 Interrupt Test Control Register
Module Base + 0x0015
Starting address location affected by INITRG register setting.
7
6
5
4
3
2
R
0
0
0
WRTINT
ADR3
ADR2
W
Reset
0
0
0
0
1
1
= Unimplemented or Reserved
Figure 5-2. Interrupt Test Control Register (ITCR)
Read: See individual bit descriptions
Write: See individual bit descriptions
1
ADR1
1
0
ADR0
1
Freescale Semiconductor
MC9S12Q128
159
Rev 1.10