XRT79L71 Datasheet, PDF (89/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
OPERATION BLOCK INTERRUPT REGISTER BIT FORMATS
OPERATION CONTROL REGISTER - BYTE 3 (ADDRESS = 0X0100)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Unused
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
XRT79L71
REV. P1.0.3
BIT 1
R/O
0
BIT 0
Configuration
Control
R/O
0
BIT NUMBER
NAME
7-6
Unused
0
Configuration Control
TYPE
R/O
R/W
DESCRIPTION
Configuration Control:
This READ/WRITE bit-field permits the user to configure the
XRT79L71 device to support any of the following configurations.
• ATM/PPP
• Clear Channel/HDLC
The following table presents the relationship between the value
written into these register bits and the corresponding Mode of
operation.
Configuration Control
0
1
Mode
ATM/PPP
Clear Channel/HDLC
OPERATION CONTROL REGISTER - BYTE 2 (ADDRESS = 0X0101)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Unused
Interrupt
WC/INT*
R/O
R/O
R/O
R/O
R/O
R/W
0
0
0
0
0
0
BIT 1
Enable
Interrupt
Auto-Clear
R/W
0
BIT 0
Interrupt
Enable
R/W
0
BIT NUMBER
NAME
7-3
Unused
2
Interrupt Write to Clear/
RUR
TYPE
R/O
R/W
DESCRIPTION
Please set to "0" for normal operation.
Interrupt - Write to Clear/RUR Select:
This READ/WRITE bit-field permits the user to configure all of
the "Source-Level" Interrupt Status bits (within the XRT79L71
device) to either be "Write to Clear" (WTC) or "Reset-upon-
Read" (RUR) bits.
0 - Configures all "Source-Level" Interrupt Status register bits to
function as "Reset-upon-Read" (RUR).
1 - Configures all "Source-Level" Interrupt Status register bits to
function as "Write-to-Clear" (WTC).
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