XRT79L71 Datasheet, PDF (36/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L71
REV. P1.0.3
PIN #
D6
NAME
RxOOF/
RxNib_1/
RxHDLCDat_1
B5
RxLCD/
RxOutClk/
RxHDLCDat_7
PRELIMINARY
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1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
TYPE
O
O
DESCRIPTION
Receive Out of Frame Indicator/Receive Nibble Interface Output pin - Bit 1/
Receive HDLC Controller Data Bus Output pin - Bit 1:
The function of this output pin depends upon whether the XRT79L71 has been
configured to operate in the Clear-Channel Framer/Nibble-Parallel Mode or the
High-Speed HDLC Controller Mode.
Clear-Channel Framer/Nibble-Parallel Mode - RxNib_1:
The XRT79L71 will output Received data from the remote terminal equipment
to the local terminal equipment via this pin, along with RxNib_0, RxNib_2 and
RxNib_3: This particular output pin functions as the LSB. The data at this pin is
updated on the rising edge of the RxClk output signal. Hence, the user's local
terminal equipment should sample this signal upon the falling edge of RxClk.
High-Speed HDLC Controller Mode - RxHDLCDat_1:
This output pin along with RxHDLCDat_[7:2] and RxHDLCDat_0 functions as
the Receive HDLC Controller byte wide output data bus. The Receive HDLC
Controller will output the contents of all HDLC frames via this output data bus,
upon the rising edge of the RxHDLCClk output signal. Hence, the user's local
terminal equipment should be designed/configured to sample this data upon the
falling edge of the RxHDLCClk output clock signal.
All other Modes - RxOOF:
The UNI Receive DS3 Framer will assert this output signal whenever it has
declared an Out of Frame (OOF) condition with the incoming DS3 frames. This
signal is negated when the framer correctly locates the F- and M-bits and
regains synchronization with the DS3 frame.
Receive Loss of Cell Delineation indicator/Receive Output Clock signal/
Receive HDLC Controller Data Bus - Bit 7 Output:
The function of output pin depends upon whether the XRT79L71 has been con-
figured to operate in the ATM, Clear-Channel Framer or High Speed HDLC Con-
troller Mode.
ATM Mode - RxLCD:
This active-high output pin will be asserted whenever the Receive Cell Proces-
sor has experienced a Loss of Cell Delineation. This pin will return "Low" once
the Receive Cell Processor has regained Cell Delineation.
Clear-Channel Framer Mode - RxOutClk:
This clock signal functions as the Transmit Payload Data Input Interface clock
source, if the XRT79L71 has been configured to operate in the loop-timing
mode.
In this mode, the local terminal equipment is expected to input data to the TxSer
input pin, upon the rising edge of this clock signal. The XRT79L71 will use the
rising edge of this signal to sample the data on the TxSer input.
High-Speed HDLC Controller Mode - RxHDLCDat_7:
This output pin along with RxHDLCDat_[6:0] functions as the Receive HDLC
Controller byte wide output data bus. This particular output pin functions as the
MSB (Most Significant Bit) of the Receive HDLC Controller byte wide data bus.
The Receive HDLC Controller will output the contents of all HDLC frames via
this output data bus, upon the rising edge of the RxHDLCClk output signal.
Hence, the user's local terminal equipment should be designed/configured to
sample this data upon the falling edge of the RxHDLCClk output clock signal.
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