XRT79L71 Datasheet, PDF (37/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L71
REV. P1.0.3
PIN #
D7
B2
D5
A2
C5
NAME
RxLOS
RxPRED
RxPOOF
RxPLOF
RxNib_0/
RxHDLCDat_0
TYPE
O
O
O
O
O
DESCRIPTION
Framer/UNI - Loss of Signal Output Indicator:
This pin is asserted when the Receive Section of the XRT79L71 encounters
180 consecutive 0's (for DS3 applications) or 32 consecutive 0's (for E3 applica-
tions) via the RxPOS and RxNEG pins. This pin will be negated once the
Receive DS3/E3 Framer has detected at least 60 "1s" out of 180 consecutive
bits (for DS3 applications) or has detected at least four consecutive 32 bit
strings of data that contain at least 8 "1s" in the receive path.
Receiver Red Alarm Indicator - Receive PLCP Processor:
The Framer/UNI asserts this output pin to denote that one of the following
events has been detected by the Receive PLCP Processor:
• OOF - Out of Frame Condition
• LOF - Loss of Frame Condition
NOTE: This output pin is only valid if the XRT79L71 has been configured to
operate in the ATM/PLCP Mode.
Receive PLCP Out of Frame Indicator:
The Receive PLCP Processor will assert this pin, when it declares an Out of
Frame condition. This output will be negated when the Receive PLCP Proces-
sor reaches the In Frame Condition.
NOTE: This output pin is only valid if the XRT79L71 has been configured to
operate in the ATM/PLCP Mode.
Receive PLCP - Loss of Frame Output Indicator:
The Receive PLCP Processor will assert this pin, when it declares a Loss of
Frame condition. This output will be negated when the Receive PLCP Proces-
sor reaches the In Frame Condition.
NOTE: This output pin is only active is the XRT79L71 has been configured to
operate in the ATM/PLCP Mode.
Receive Nibble Interface Output pin - Bit 0/Receive HDLC Controller Data
Bus output pin - Bit 0:
The function of this output pin depends upon whether the XRT79L71 has been
configured to operate in the Clear-Channel/Nibble-Parallel Mode, the High-
Speed HDLC Controller Mode, or in some other mode.
Clear-Channel/Nibble-Parallel Mode - RxNib_0:
The XRT79L71 will output Received data from the remote terminal equipment
to the local terminal equipment via this pin, along with RxNib_1 through
RxNib_3. This particular output pin functions as the LSB.
The data at this pin is updated on the rising edge of the RxClk output signal.
Hence, the user's local terminal equipment should sample this signal upon the
falling edge of RxClk.
High-Speed HDLC Controller Mode - RxHDLCDat_0:
This output pin along with RxHDLCDat_[7:1] functions as the Receive HDLC
Controller byte wide output data bus. This particular output pin functions as the
LSB (Least Significant Bit) of the Receive HDLC Controller byte wide data bus.
The Receive HDLC Controller will output the contents of all HDLC frames via
this output data bus, upon the rising edge of the RxHDLCClk output signal.
Hence, the user's local terminal equipment should be designed/configured to
sample this data upon the falling edge of the RxHDLCClk output clock signal.
NOTE: This output pin is only active if the XRT79L71 is configured to operate in
the Clear-Channel/Nibble-Parallel Mode or in the High-Speed HDLC
Controller Mode. This output is inactive for all remaining modes.
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