XRT79L71 Datasheet, PDF (31/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L71
REV. P1.0.3
PIN #
R3
M4
NAME
TxUPrty/
TxPPrty
TxUEN/
TxPEN
TYPE
DESCRIPTION
I Transmit UTOPIA Data Bus - Parity Input/Transmit POS-PHY Interface - Par-
ity Input:
The function of this input pin depends upon whether the XRT79L71 has been
configured to operate in the ATM UNI or PPP Mode.
ATM UNI Mode - TxUPrty:
The ATM Layer processor will apply the parity value of the byte or word which is
being applied to the Transmit UTOPIA Data Bus (e.g., TxUData[7:0] or TxU-
Data[15:0]) inputs of the XRT79L71, respectively.
NOTE: This parity value should be computed based upon the odd-parity of the
data applied at the Transmit UTOPIA Data Bus.
The Transmit UTOPIA Interface block within the XRT79L71 will independently
compute an odd-parity value of each byte (or word) that it receives from the ATM
Layer processor and will compare it with the logic level of this input pin.
PPP Mode - TxPPrty:
The Link Layer Processor will apply the parity value of the byte or word which is
being applied to the Transmit POS-PHY Data Bus (e.g., TxPData[7:0] or TxP-
Data[15:0]) inputs of the XRT79L71, respectively.
NOTE: This parity value should be computed based upon the odd-parity of the
data applied to the Transmit POS-PHY Data Bus. The Transmit POS-
PHY Interface block within the XRT79L71 will independently compute an
odd-parity value of each byte (or word) that it receives from the Link
Layer processor and will compare it will the logic level of this input pin.
I Transmit UTOPIA Interface Block - Write Enable/Transmit POS-PHY Interface -
Write Enable:
The function of this input pin depends upon whether the XRT79L71 has been
configured to operate in the ATM UNI or PPP Mode.
ATM UNI Mode Operation - TxUEN:
This active-low signal, from the ATM Layer processor enables the data on the
Transmit UTOPIA Data Bus to be written into the TxFIFO on the rising edge of
TxUClk. When this signal is asserted, then the contents of the byte or word that
is present, on the Transmit UTOPIA Data Bus, will be latched into the Transmit
UTOPIA Interface block, on the rising edge of TxUClk.
When this signal is negated, then the Transmit UTOPIA Data bus inputs will be
tri-stated.
PPP Mode Operation - TxPEN:
This active-low signal, from the Link Layer processor enables the data on the
Transmit POS-PHY Data Bus to be written into the TxFIFO on the rising edge of
TxPClk. When this signal is asserted, then the contents of the byte or word that
is present, on the Transmit POS-PHY Data Bus, will be latched into the Transmit
POS-PHY Interface block, on the rising edge of TxPClk.
When this signal is negated, then the Transmit POS-PHY Data bus inputs will be
tri-stated.
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