XRT79L71 Datasheet, PDF (123/441 Pages) Exar Corporation – 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L71
REV. P1.0.3
DS3/E3 FRAMER BLOCK REGISTERS
The register map for the DS3/E3 Framer Block is presented in the Table below. Additionally, a detailed
description of each of the "DS3/E3 Framer" block registers is presented below.
OPERATING MODE REGISTER (DIRECT ADDRESS = 0X1100)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Local Loop
Back
IsDS3
Internal LOS
Enable
RESET
Interrupt
Enable
RESET
R/W
R/W
R/W
R/W
R/W
0
0
1
0
1
BIT 2
Frame Format
R/W
0
BIT 1
BIT 0
TimRefSel[1:0]
R/W
R/W
1
1
BIT NUMBER
NAME
7
Local Loop Back
6
IsDS3
TYPE
R/W
R/W
DESCRIPTION
Framer Block Local Loop-back Mode:
This READ/WRITE bit field configures the Frame Generator/
Frame Synchronizer blocks to operate in the Local Loop-back
Mode. If the Frame Generator/Frame Synchronizer blocks are
configured to operate in the Local Loop-back Mode, then the
TxPOS, TxNEG and TxLineClk signal is internally looped back
into the RxPOS, RxNEG and RxLineClk signals.
0 - Normal Operating Mode
1 - Local Loop-back Mode
Is DS3 Mode:
This READ/WRITE bit-field, along with Bit 2 (Frame Format),
permits the user to configure the Frame Generator/Frame Syn-
chronizer block to operate in the appropriate framing format.
The relationship between the state of this bit-field, Bit 2 and the
resulting framing format is presented below.
Bit 6 (IsDS3)
0
0
1
1
Bit 2 (Fram e
Form at)
0
1
0
1
Fram ing Form at
E3, ITU-T G.751
E3, ITU-T G.832
DS3, C-bit Parity
DS3, M13
5
Internal LOS Enable
R/W Internal LOS Enable:
This READ/WRITE bit-field permits the user to enable or disable
the "Internal LOS Detector", within the Frame Synchronizer
block.
0 - Internal LOS Detector is disabled.
1 - Internal LOS Detector is enabled.
NOTE: The Internal LOS Detector only functions if the Channel
is configured to operate in the Dual-Rail Mode. If the
Channel is configured to operate in the Single-Rail
Mode, then the Internal LOS Detector will be disabled.
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